We describe a heuristic scheduling approach for optimizing floating-point pipelines subject to input port constraints. The objective\r\nof our technique is to maximize functional unit reuse while minimizing the following performance metrics in the generated circuit:\r\n(1) maximum multiplexer fanin, (2) datapath fanout, (3) number of multiplexers, and (4) number of registers. For a set of systems\r\nbiology markup language (SBML) benchmark expressions, we compare the resource usages given by our method to those given by\r\na branch-and-bound enumeration of all valid schedules. Compared with the enumeration results, our heuristic requires on average\r\n33.4% lessmultiplexer bits and 32.9% less register bits than the worse case, while only requiring 14% moremultiplexer bits and 4.5%\r\nmore register bits than the optimal case. We also compare our results against those given by the state-of-art high-level synthesis\r\ntool Xilinx AutoESL. For the most complex of our benchmark expressions, our synthesis technique requires 20% less FPGA slices\r\nthan AutoESL.
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